The invention is directed to an improved approach for designing, testing, and manufacturing integrated circuits.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An electronic design automation (EDA) system or computer aided design (CAD) tools receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example. The circuit design is then transformed into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files are used to produce patterns called masks by an optical or electron beam pattern generator. Subsequently, during fabrication of the IC, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the IC are therefore formed on the wafer in accordance with the patterns.
Rapid developments in the technology and equipment used to manufacture semiconductor ICs have allowed electronics manufacturers to create smaller and more densely packed chips in which the IC components, such as wires, are located very close together. When electrical components are spaced too close together, the electrical characteristics or operation of one component may affect the electrical characteristics or operation of its neighboring components.
Electrical analysis is typically performed to verify and check the electrical behavior and performance of the circuit design. For example, analysis is performed on the circuit design to obtain capacitance and resistance for specific geometric descriptions of conductors in the design, creating an estimation of the capacitance and resistance from a process which is called parasitic resistance and capacitance (RC) extraction. A RC analysis tool comprises software and/or hardware that translates a geometric description of conductor and insulator objects, or other shapes described in an IC design file or database, to associated parasitic capacitance values. The capacitance values may include total capacitance of a single conductor, defined as the source conductor, relative to neighboring conductors or separate coupling capacitance between the source and one or more neighboring conductors.
Many processing steps are employed when fabricating an integrated circuit. For example, chemical mechanical polishing (CMP) is a very important step that is used to form interconnects on the manufactured IC. In addition, etch processing is typically employed in which the lithographic patterns that define the dimensions of the circuitry are physically etched into the wafer surface or other thin films deposited on the wafer surface. Etch equipment includes mechanisms to selectively remove materials (e.g., oxide) from a wafer surface or thin films on the wafer surface patterned with lithography equipment. Metal deposition is a process step in a copper damascene flow that is used to deposit copper material within the interconnect structures.
However, significant variations may arise during the process of manufacturing the IC, such as variations in feature density, widths, and heights caused by lithography, etch, CMP, and/or deposition processes. For example, variations based upon CMP and etching processes are often caused by dielectric loss, dishing, erosion, or other metal losses.
These variations may cause significant differences between the intended dimensions of the circuit features and the as-manufactured dimensions of those features on a fabricated circuit product. The problem is that if the electrical analysis, such as RC extraction, is performed using the as-designed dimensions, then the analysis results will be incorrect if the as-manufactured dimensions are significantly different.